Power optimization is a very important and challenging step in the physical design flow,\nand it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many\ntechniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet\nthe power requirement. In this paper, we will evaluate, independently from the library file, the impact\nof redefining the max transition constraint (MTC) before the power optimization phase, and we will\nstudy the impact of over-constraining or under-constraining a design on power in order to find the\nbest trade-off between design constraining and power optimization. Experimental results showed\nthat power optimization depends on the applied MTC and that the MTC value corresponding to\nthe best power reduction results is different from the default MTC. By using a new MTC definition\nmethod on several designs, we found that the power gain between the default methodology and the\nnew one reaches 2.34%.
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